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ARM EN0-001 ARM Accredited Engineer Exam Practice Test

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Total 210 questions
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ARM Accredited Engineer Questions and Answers

Question 1

Which of the following processors includes a Generic Interrupt Controller as a standard component?

Options:

A.

Cortex-A8

B.

Cortex-M3

C.

Cortex-R4F

D.

Cortex-A9 MPCore

Question 2

A simple system comprises of the following memory map:

Flash - 0x0 to 0x7FFF

RAM - 0x10000 to 0X17FFF

When conforming to the ABI, which of the following is a suitable initial value for the stack pointer?

Options:

A.

Top address of RAM (0x18000)

B.

Top address of flash (0x8000)

C.

Bottom address of RAM (0x10000)

D.

Bottom address of flash (0x0000)

Question 3

In general, when programming in C, stack accesses will be reduced by:

Options:

A.

Disabling inlining.

B.

Never passing more than four parameters in function calls.

C.

Declaring automatic variables as "packed".

D.

Configuring the compiler to optimize for space.

Question 4

Which ARMv7 instructions are recommended to implement a semaphore?

Options:

A.

SWP, SWPB

B.

TEQ, TST

C.

STC, SBC

D.

LDREX, STREX

Question 5

When using an Operating System, which instruction is used by user code to request a service from the kernel?

Options:

A.

BLX

B.

RFEFD

C.

SRSFD

D.

SVC

Question 6

In a multi-processor system, there are four processors numbered 0, 1, 2 and 3. The state of the processors is as follows:

  • CPU 0 and 1 are sleeping in low-power state following a WFI instruction. . CPU 2 is executing program code.
  • CPU 3 is sleeping in low-power state following a WFE instruction.

CPU 2 executes a SEV instruction. What is the effect on the system?

Options:

A.

CPU 0: executing, CPU 1: executing, CPU 2: executing. CPU 3: executing

B.

CPU 0: executing, CPU 1: executing. CPU 2: executing. CPU 3: sleeping

C.

CPU 0: sleeping, CPU 1: sleeping. CPU 2: executing. CPU 3: executing

D.

CPU 0: sleeping, CPU 1: sleeping. CPU 2: sleeping, CPU 3: executing

Question 7

The following ARM instruction can be used to return from an exception:

movs pc, lr

Apart from the program counter, which register is updated by this instruction?

Options:

A.

Ir

B.

r0

C.

CPSR

D.

SCTLR

Question 8

Capturing processor execution trace is characterized as being:

Options:

A.

Influenced by breakpoints.

B.

Intrusive on normal processor operation.

C.

Inaccurate regarding code execution history.

D.

Not intrusive on normal processor operation.

Question 9

Which one of the following statements best describes the function of vector catch logic?

Options:

A.

It traps writes to the memory containing the vector table

B.

It provides additional resources for debugging exception handlers

C.

It provides configurable exception priorities on an ARM processor

D.

It provides an improved mechanism for an application to handle exceptions

Question 10

Which of the following statements is TRUE with respect to the power consumption related to memory accesses?

Options:

A.

Accessing a large memory device consumes less power than accessing a small one

B.

A series of non-sequential accesses is more efficient than a series of sequential accesses

C.

Increasing the size of the cache will always reduce power consumption for a given application

D.

Storing frequently used data in Tightly Coupled Memory will reduce power consumption

Question 11

Clicking the Start button in a debugger:

Options:

A.

Begins processor execution.

B.

Resets the processors.

C.

Erases existing breakpoints.

D.

Puts the processor(s) into debug state.

Question 12

In a single-processor system, which of these operations requires a barrier instruction to guarantee correct operation?

Options:

A.

Copying data from Flash to RAM

B.

Changing from one privileged mode to another

C.

Loading code into memory and then executing it

D.

Incrementing a RAM location that will be read by an interrupt handler

Question 13

Which THREE of the following items should be preserved by software when entering dormant mode? (Choose three)

Options:

A.

Current Program Status Register (CPSR)

B.

Contents of the Level 2 data cache

C.

The Floating Point Status and Control Register (FPSCR)

D.

All User mode general-purpose registers

E.

The CP15 Multiprocessor Affinity Register

F.

Contents of the Level 1 data cache

Question 14

Which of the following operations would count as intrusive to normal processor operation?

Options:

A.

Tracing using Embedded Trace Macrocell (ETM)

B.

Halt mode debugging

C.

Monitor mode debugging

D.

Using the Performance Monitor Unit

Question 15

Consider the following instruction sequence:

STR r0, [r2] ; instruction A

DSB

ADD r0, r1, r2 ; instruction B

LDR r3, [r4] ; instruction C

SUB r5, r6, #3 ; instruction D

At what point will execution pause until the STR access is complete?

Options:

A.

After instruction A and before the DSB

B.

After the DSB and before instruction B

C.

After instruction B and before instruction C

D.

After instruction C and before instruction D

Question 16

Assume a multicore processor with coherency management based on the MESI protocol. When a core changes the contents of a shared cache line, what is the final status of that line in the local cache?

Options:

A.

Modified

B.

Exclusive

C.

Shared

D.

Invalid

Question 17

An ARM processor connected to a Generic Interrupt Controller (GIC) is handling an active interrupt 11. A new interrupt 12 that is received at the GIC is forwarded to the processor, and the active interrupt 11 is preempted. Which of the following possible values of 11's priority (P1), 12's priority (P2) and the processor’s priority mask (PM) permit this to happen? Assume there are 256 priority levels implemented.

Options:

A.

P1 = 0x0F, P2 = 0x10, PM = 0xFF

B.

P1 = 0x10, P2 = 0x0F, PM = 0xFF

C.

P1 =0x0F, P2 = 0x10. PM = 0x0

D.

P1 = 0x10, P2 = 0x0F, PM = 0x0

Question 18

Which of the following will cause the ARM Compiler to target the Thumb instruction set?

Options:

A.

Compiling exception handlers

B.

Specifying a Thumb-capable processor (e.g. -cpu=Cortex-A9)

C.

Enabling Thumb code generation on the command line (--thumb)

D.

Configuring the compiler for maximum code density (-Ospace)

Question 19

In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)

Options:

A.

VA == PA; No address translations; instructions and data are not cached

B.

VA! = PA; No address translations; instructions may be cached but not data

C.

VA == PA; Address translations take place; data may be cached but not instructions

D.

VA == PA; No address translations; instructions may be cached but not data

Question 20

Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

Options:

A.

5 cycles

B.

7 cycles

C.

8 cycles

D.

15 cycles

Question 21

Which of the following memory attributes, specified in a translation table entry, could be used to protect a page containing a read-sensitive peripheral from speculative instruction fetches?

Options:

A.

S (Secure)

B.

nG (non-Global)

C.

xN (Execute Never)

D.

AP (Access Permission)

Question 22

What side-effect could using a debugger to read memory contents have?

Options:

A.

The memory contents could be set to zero

B.

Some memory contents could be rewritten

C.

The processor MMU pagetables could be modified

D.

The processor cache could be cleaned or/and invalidated

Question 23

When the processor is executing in Thumb state, which of the following statements is correct about the values stored in R15?

Options:

A.

Bits[31:16] are duplicated with bits[15:0]

B.

The PC value is stored in bits[31:1] and bit[0] is treated as zero

C.

The PC value is stored in bits[31:16] and bits[15:0] are undefined

D.

The PC value is stored in bits[15:0] and bits[31:16] are undefined

Question 24

In a loop termination test, how might a programmer indicate to the compiler that the loop iteration count limit is divisible by four?

Options:

A.

AND the count limit with -0x3

B.

Add 4 to the count limit

C.

Subtract 4 from the count limit

D.

Shift the count limit left two bit positions

Question 25

When debugging an embedded Linux system, which one of the following techniques can be used to halt a single user thread, while allowing other threads to continue to run during the debug process?

Options:

A.

Halting a single user thread in an embedded Linux system is not possible

B.

Use the Linux kernel printk() function to output messages to the console

C.

Connect a Linux-aware JTAG debugger to the target, which allows single-stepping of the code

D.

Connect a debugger running on an external host device to an instance of gdbserver running on the target, using Ethernet

Question 26

Under which of the following circumstances would a DSB instruction be used?

Options:

A.

In a multi-threaded system, when two threads need to be synchronized at a particular point

B.

When accessing a peripheral, it is necessary to halt until the memory access is complete

C.

When it is necessary to temporarily disable interrupts while carrying out a particular memory access

D.

In a multiprocessor system, when it is necessary to halt one of the cores while the other completes a critical task

Question 27

In which TWO of the following locations would a compiler typically place local variables? (Choose two)

Options:

A.

ROM

B.

Heap

C.

Cache

D.

Registers

E.

Stack

Question 28

Under which of the following data-sharing scenarios would cache maintenance operations be necessary?

Options:

A.

Sharing data with another thread running on the same core

B.

Sharing data with another process running on the same core

C.

Sharing data with an external device

D.

Sharing data with another CPU in an SMP system

Question 29

For Cortex-A series cores, what instruction(s) are recommended to implement a mutex or semaphore?

Options:

A.

SWP and SWPB

B.

DSB and ISB

C.

LDREX and STREX

D.

DMB

Question 30

In an ARMv7-A processor that includes the Advanced SIMD extension (NEON), where are the data values operated on by NEON instructions stored?

Options:

A.

In system memory

B.

In registers shared with the VFP register set

C.

In registers shared with the integer register set

D.

In dedicated registers not shared with other registers

Question 31

The Performance Monitoring Unit (PMU) of a Cortex-A9 processor permits direct measurement of which one of the following?

Options:

A.

Cache Size

B.

Clock Speed

C.

Program size

D.

Numbers of instructions executed

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